Senior ASIC Design Engineer — AI Evaluation & Benchmarks

We’re looking for an experienced chip design engineer to evaluate Mistral models on real-world semiconductor design workflows. You’ll combine hands-on engineering expertise with benchmark development and technical review to improve how AI models perform tasks across RTL development, synthesis, physical design, and tapeout.

What You’ll Do

Evaluate AI model performance: Assess recent Mistral models on chip design tasks, identifying errors, limitations, and opportunities to improve technical accuracy and practical usefulness.Develop chip design benchmarks: Scope realistic tasks with clear requirements, appropriate difficulty levels, reference solutions, and measurable evaluation criteria.Review vendor-delivered tasks: Validate tasks involving RTL coding, logic synthesis, and synthesized netlists for correctness, completeness, reproducibility, and relevance to engineering workflows.Guide synthetic task generation: Provide domain expertise across the design flow, from RTL coding and verification through physical design, timing closure, and tapeout.Create high-quality seed tasks: Develop original chip design problems, supporting artifacts, and reference solutions to seed synthetic task generation.Define quality standards: Establish review criteria that account for functional correctness, synthesizability, timing constraints, and power, performance, and area.Collaborate with AI and data teams: Translate engineering findings into actionable feedback that improves model evaluations and generated training data. What You Bring

Significant hands-on experience in ASIC or SoC design, with deep expertise in RTL development and synthesis.Strong proficiency in Verilog or SystemVerilog, including writing, debugging, and reviewing synthesizable RTL.Experience with EDA tools for simulation, synthesis, and implementation, including interpreting reports and diagnosing design issues.Working knowledge of the RTL-to-GDSII flow, including static timing analysis, physical design, timing closure, and signoff.Ability to create self-contained engineering tasks with clear specifications, testbenches or validation methods, and technically sound reference solutions.Strong technical judgment and attention to detail when reviewing code, netlists, constraints, and design artifacts.Clear written communication and the ability to explain complex design concepts to AI researchers, engineers, and data teams. Preferred Qualifications

Experience contributing to a chip design through tapeout.Experience evaluating AI-generated code or developing technical benchmarks, datasets, or automated validation workflows.Proficiency in Python, Tcl, or shell scripting for EDA automation and results analysis.Familiarity with formal verification, equivalence checking, or open-source chip design tools.